Carbon nanotube technologies are beginning to make a significant impact on the electronic device industry. As is known to those having ordinary skill in the art, single-wall carbon nano-tubes are quasi one-dimensional nano-scale wires. Such tubes can demonstrate metallic or semiconducting properties depending on their chirality and radius. One new area of implementation is that of non-volatile memory devices. One such application is described in U.S. Pat. No. 6,574,130 which is directed to hybrid circuits using nanotube electromechanical memory. This reference is hereby incorporated by reference for all purposes. Such nanotube electromechanical memory devices are also described in detail in WO 01/03208 which is incorporated by reference in its entirety. A fuller description of the operation of these devices can be obtained in these references.
These hybrid memory devices make use of nanotubes operating as mechanical switches that can be switched on and off by electrodes. The nanotubes operate by having an air gap above and below the nanotubes. The electrodes are selectively biased to bend the nanotubes to make electrical contact (or not) with various electrical contacts of a memory cell in order to set a memory state for the memory cell. Thus, any partial filling of the air gaps impairs the operation of the memory cell. Current fabrication methods and structures are less effective than desired.
An example of a current method of constructing such a hybrid memory cell is described with respect to FIGS. 1(a)-1(d). Referring to FIG. 1(a), a substrate 101 has a transistor formed thereon. As depicted the transistor has diffusion regions 101d and a gate electrode 101g. Over the transistor is formed a dielectric layer 102 that typically includes electrical connects with the transistor and other circuit elements. For example a conductive via 103. Over this substrate is formed a first nitride layer 111 having a lower opening 112a that is filled with polysilicon sacrificial material. Over the sacrificial material is formed a nanotube electrical contact 113 that spans the lower opening 112a. This nanotube electrical contact 113 is electrically connected with other circuit elements. Over this substrate is formed an oxide layer 114 having an upper opening 112b that is filled with polysilicon sacrificial material. Thus, the upper sacrificial material is formed over the nanotube electrical contact 113. Typically, another nitride layer and an electrode 115 are formed over the upper sacrificial material 112b (and the underlying nanotube electrical contact 113).
Further processing requires that the sacrificial layers be removed and that the substrate be covered with a thick passivation layer. In current processes, this has proven a difficult problem to solve. The sacrificial layers must be removed first to create an air gap above and below the nanotube electrical contact. Referring to FIG. 1(b) a TMAH (tetramethyl ammonium hydroxide) wet etch is used to remove the sacrificial layers 112a, 112b underlying the electrode 115. This allows the formation of a lower air gap 122a and an upper air gap 122b. Thus, the nanotube electrical contact 113 now has underlying and overlying air gaps. This substrate must now be passivated. The problem is that the passivation materials have a tendency to fill the air gaps during passivation. This is detrimental to the operation of the device and therefore must be addressed.
FIGS. 1(c) and 1(d) refer to current solution to this passivation underfill problem. A thin “sealing” layer 123 of sputter deposited silicon dioxide (SiO2) is used to form a layer that seals the air gap chambers. Subsequently, a thick layer of passivation material is used to form an interlayer dielectric layer (ILD layer). Although such a process can be used to fabricate air gaps, such a process is fraught with numerous process limitations and disadvantageous. For one, oxide sputtering processes do not easily integrate into the standard CMOS integration and process schemes used to fabricate the rest of the substrate. Additionally, and probably more importantly, the SiO2 sputter deposition process used to seal the air gap chambers tends to fill the chambers to some extent. This chamber filling is contrary to the purpose of this step. Moreover, even partial filling of the air gap chambers puts a lower limit on the size of such chambers (i.e., the chambers must be of a certain size to accommodate the degree of filling caused by the SiO2 sputtering.
Present processes for fabricating air gap chambers for use with nanotube structures present some problems which have not yet been successfully addressed in the industry. Accordingly, there is a need for process methods capable of reliable and repeatable fabrication of functional air gap chambers usable with nanotube crossbar structures such as memory cells and other structures for use in integrated circuits. Additionally, there is a need for new nano-scale electromechanical circuit structures and air gap chamber structures.